RegViz: Visualize CH1C1 Bitfield

NXP Semiconductors /MK64F12 /PDB0 /CH1C1

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Interpret as CH1C1

EN3=0, EN2=0, EN1=0, BB0=0, TOS4=0, EN6=0, TOS6=0, EN5=0, BB6=0, EN0=0, EN7=0, BB2=0, BB3=0, TOS3=0, BB1=0, TOS2=0, BB5=0, BB4=0, TOS7=0, TOS5=0, TOS0=0, EN4=0, BB7=0, TOS1=0

Description

Channel n Control register 1

Fields

EN0	PDB Channel Pre-Trigger Enable 0 (0): PDB channel’s corresponding pre-trigger disabled. 1 (1): PDB channel’s corresponding pre-trigger enabled.
EN1	PDB Channel Pre-Trigger Enable 0 (0): PDB channel’s corresponding pre-trigger disabled. 1 (1): PDB channel’s corresponding pre-trigger enabled.
EN2	PDB Channel Pre-Trigger Enable 0 (0): PDB channel’s corresponding pre-trigger disabled. 1 (1): PDB channel’s corresponding pre-trigger enabled.
EN3	PDB Channel Pre-Trigger Enable 0 (0): PDB channel’s corresponding pre-trigger disabled. 1 (1): PDB channel’s corresponding pre-trigger enabled.
EN4	PDB Channel Pre-Trigger Enable 0 (0): PDB channel’s corresponding pre-trigger disabled. 1 (1): PDB channel’s corresponding pre-trigger enabled.
EN5	PDB Channel Pre-Trigger Enable 0 (0): PDB channel’s corresponding pre-trigger disabled. 1 (1): PDB channel’s corresponding pre-trigger enabled.
EN6	PDB Channel Pre-Trigger Enable 0 (0): PDB channel’s corresponding pre-trigger disabled. 1 (1): PDB channel’s corresponding pre-trigger enabled.
EN7	PDB Channel Pre-Trigger Enable 0 (0): PDB channel’s corresponding pre-trigger disabled. 1 (1): PDB channel’s corresponding pre-trigger enabled.
TOS0	PDB Channel Pre-Trigger Output Select 0 (0): PDB channel’s corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 1 (1): PDB channel’s corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
TOS1	PDB Channel Pre-Trigger Output Select 0 (0): PDB channel’s corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 1 (1): PDB channel’s corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
TOS2	PDB Channel Pre-Trigger Output Select 0 (0): PDB channel’s corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 1 (1): PDB channel’s corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
TOS3	PDB Channel Pre-Trigger Output Select 0 (0): PDB channel’s corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 1 (1): PDB channel’s corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
TOS4	PDB Channel Pre-Trigger Output Select 0 (0): PDB channel’s corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 1 (1): PDB channel’s corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
TOS5	PDB Channel Pre-Trigger Output Select 0 (0): PDB channel’s corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 1 (1): PDB channel’s corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
TOS6	PDB Channel Pre-Trigger Output Select 0 (0): PDB channel’s corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 1 (1): PDB channel’s corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
TOS7	PDB Channel Pre-Trigger Output Select 0 (0): PDB channel’s corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 1 (1): PDB channel’s corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
BB0	PDB Channel Pre-Trigger Back-to-Back Operation Enable 0 (0): PDB channel’s corresponding pre-trigger back-to-back operation disabled. 1 (1): PDB channel’s corresponding pre-trigger back-to-back operation enabled.
BB1	PDB Channel Pre-Trigger Back-to-Back Operation Enable 0 (0): PDB channel’s corresponding pre-trigger back-to-back operation disabled. 1 (1): PDB channel’s corresponding pre-trigger back-to-back operation enabled.
BB2	PDB Channel Pre-Trigger Back-to-Back Operation Enable 0 (0): PDB channel’s corresponding pre-trigger back-to-back operation disabled. 1 (1): PDB channel’s corresponding pre-trigger back-to-back operation enabled.
BB3	PDB Channel Pre-Trigger Back-to-Back Operation Enable 0 (0): PDB channel’s corresponding pre-trigger back-to-back operation disabled. 1 (1): PDB channel’s corresponding pre-trigger back-to-back operation enabled.
BB4	PDB Channel Pre-Trigger Back-to-Back Operation Enable 0 (0): PDB channel’s corresponding pre-trigger back-to-back operation disabled. 1 (1): PDB channel’s corresponding pre-trigger back-to-back operation enabled.
BB5	PDB Channel Pre-Trigger Back-to-Back Operation Enable 0 (0): PDB channel’s corresponding pre-trigger back-to-back operation disabled. 1 (1): PDB channel’s corresponding pre-trigger back-to-back operation enabled.
BB6	PDB Channel Pre-Trigger Back-to-Back Operation Enable 0 (0): PDB channel’s corresponding pre-trigger back-to-back operation disabled. 1 (1): PDB channel’s corresponding pre-trigger back-to-back operation enabled.
BB7	PDB Channel Pre-Trigger Back-to-Back Operation Enable 0 (0): PDB channel’s corresponding pre-trigger back-to-back operation disabled. 1 (1): PDB channel’s corresponding pre-trigger back-to-back operation enabled.

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